WDEN=STOP, WDRESET=INTERRUPT, WDPROTECT=FLEXIBLE
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
| WDEN | Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. 0 (STOP): Stop. The watchdog timer is stopped. 1 (RUN): Run. The watchdog timer is running. |
| WDRESET | Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 0 (INTERRUPT): Interrupt. A watchdog time-out will not cause a chip reset. 1 (RESET): Reset. A watchdog time-out will cause a chip reset. |
| WDTOF | Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. |
| WDINT | Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. |
| WDPROTECT | Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 0 (FLEXIBLE): Flexible. The watchdog time-out value (TC) can be changed at any time. 1 (THRESHOLD): Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. |
| LOCK | Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |